Creating a cache memory benchmark in VHDL

Creating a cache memory benchmark in VHDL

I have a working VHDL design for Data&Instruction Caches. I want to
evaluate it (find miss rates and so) with a testbench.
So I want to know how to create random requests to the caches? and how to
make them favor some type of locality or have a pattern (like sequential
access but with occasional random jumps in a program for example)?
In other words, how to make a VHDL Benchmark to evaluate the cache designs
in different conditions and memory access patterns?